The present invention relates to latching comparator circuits. More specifically, the present invention relates to a novel analog voltage comparator circuit having hysteresis latching capability with respect to a reference voltage.
In many applications, it is necessary to provide a circuit which provides an output signal of one of two output levels dependent upon the input signal. In harsh electrical environments such as found in automobile electronics, the input signal may be plagued with switch bounce transients and glitches which could result in erroneous output levels from the comparator circuit. In addition, some amount of hysteresis about a threshold voltage is preferred in the detection of the input signal for changing the state of the output signal.
Latching comparators are known within the digital logic field so as to latch an input data signal, which is either high or low, as an output signal. However, these digital circuits respond only to the predetermined high and low levels of the input signal and are not sufficiently flexible to provide hysteresis about a predetermined reference voltage. In summary, the circuits used in digital logic are ineffective for providing switch debounce capability so as to latch an output signal when the input signal makes a first crossing of a threshold in relation to a reference voltage.